Board — Accelerator Silicon (GPU / TPU / ASIC / Wafer-Scale)

Status: active Owner: Finance / Charlie AGT-002 Board ID: BOARD-AI-SILICON Visibility: PUBLIC Last updated: 2026-07-10

Purpose

Track the technical trajectory of AI accelerator silicon — architectures, roadmaps, measured performance, and cost curves — across the merchant GPU incumbents, hyperscaler in-house ASICs, the China domestic stack, and wafer-scale challengers.

Methodology (SemiAnalysis-inspired, public-primitives version): follow the physical primitives — process node, memory type/bandwidth, packaging, scale-up/scale-out interconnect, rack power — from PUBLIC primary sources only (vendor spec pages, architecture whitepapers, MLCommons results, listed-company filings). Spec-sheet numbers are commitments (A2); measured benchmark results and shipment/revenue disclosures are throughput (A3); street pricing and rental rates are price signals (A4).

This board's pages are approved PUBLIC (Hugo, 2026-07-10): technical facts and source-graded tables only. Investment implications, share forecasts, and portfolio linkage stay MEMBERS/INTERNAL elsewhere.

Coverage

Tracked Series

Primary Sources

• Vendor spec pages / architecture whitepapers (NVIDIA, AMD, Google Cloud, Huawei, Cambricon IR, Cerebras) — Primary
• MLCommons (MLPerf Training/Inference) results tables — Primary
• Listed-company filings: Cambricon 688256.SH (cninfo), TSMC/SK Hynix calls for node/HBM context — Primary
• SemiAnalysis FREE posts — Secondary (never paywalled content; client-conflict caveat)
• Hot Chips / ISSCC papers — Primary for architecture detail

Current Claims

• CLAIM-AI-SILICON-001 — custom-ASIC share of accelerator compute rising vs merchant GPU (watch)
• CLAIM-AI-SILICON-002 — China domestic stack node gap vs frontier, and the cluster-scale/chiplet workaround path (watch)
• Related: CLAIM-AI-BOTTLENECK-001 (pricing power sits at the current bottleneck)

Noise Rules

• Ignore un-dated "next-gen chip will be Nx faster" claims without a spec sheet or paper (A1 narrative — log nothing).
• Peak-FLOPs marketing without precision/sparsity qualifiers is not comparable data; record only with precision noted.
• Do not infer China-stack parity from single benchmark demos; require reproducible results or filings-visible revenue.
• Vendor "orders/backlog" leaks are not shipments; only filings and disclosed shipments count as A3.

Series — Accelerator Spec Matrix

Owner: Finance / Charlie AGT-002 Source ID: SRC-AI-VENDOR-SPECS (vendor spec pages / whitepapers), SRC-AI-CNINFO-FILINGS (China stack) Unit: mixed — process node, memory GB, bandwidth TB/s, dense FLOPs by precision, TDP W, interconnect GB/s Cadence: event-driven (launches) + quarterly sweep Visibility: PUBLIC As-of convention: every row carries the as-of date the spec was verified and a source grade; peak FLOPs must state precision (and sparsity if applicable)

How to append: one row per chip per verification pass. When a vendor revises a spec (e.g. memory config bump), append a NEW row with the new as-of date — do not edit old rows. Status values: shipping | announced | rumored (rumored rows require grade 🟠 or worse and are excluded from public claim support).

Series — Accelerator Measured Benchmarks

Owner: Finance / Charlie AGT-002 Source ID: SRC-AI-MLCOMMONS (MLPerf Training/Inference), vendor reproducible disclosures Unit: benchmark-native (time-to-train, tokens/s, samples/s); perf-per-chip and perf-per-watt derived where system size is disclosed Cadence: per MLPerf round (~2 per year) + event-driven vendor disclosures Visibility: PUBLIC As-of convention: every row carries the MLPerf round or disclosure date and a source grade; derived perf/$ uses list or disclosed pricing with the price source noted

How to append: prefer MLCommons closed-division results (Primary). Vendor self-reported numbers outside MLPerf are 🟡 at best and must be labeled. Never compare across precisions or divisions without noting it.