Research library ยท updated 2026-07-10 ยท public

Entity โ€” Google TPU

Status: active Owner: Finance / Charlie AGT-002 Entity ID: ENTITY-AI-GOOGLE-TPU Visibility: PUBLIC Last verified: 2026-07-10

Snapshot

Google's TPU line is the most mature hyperscaler in-house ASIC program (seven generations) and the only one sold broadly as a cloud product at scale. The latest generally-available chip is TPU v7 "Ironwood" (TPU7x): 4.614 PF FP8 per chip, 192 GB HBM3e, pods to 9,216 chips โ€” the first TPU pitched head-on at frontier training and high-volume inference against Blackwell-class GPUs. Broadcom co-design of TPUs is widely reported and reflected in Broadcom's disclosed custom-AI-silicon revenue, though Google does not name partners on spec pages.

Chip Table

ChipStatusKey spec highlightsAs-ofSourceGrade
TPU v7 Ironwood (TPU7x)shipping (GA on Google Cloud)4.614 PF FP8 / 2.307 PF BF16 per chip; 192 GB HBM3e at 7.37 TB/s; ICI 1.2 TB/s bidirectional per chip; dual-chiplet (2 TensorCores + 4 SparseCores); pods to 9,216 chips (42.5 EF FP8 per pod, vendor)2026-07-10https://docs.cloud.google.com/tpu/docs/tpu7x๐ŸŸข
TPU v6e Trilliumshipping918 TF BF16 / 1,836 TOPS INT8 per chip; 32 GB HBM at 1.64 TB/s; ICI 800 GB/s; 256-chip pod2026-07-10https://docs.cloud.google.com/tpu/docs/v6e๐ŸŸข
TPU v8 (next gen)rumoredpress reports of an eighth generation split into separate training and inference chips on TSMC 2nm-class node; no official documentation2026-07-10https://thenextweb.com/news/google-ironwood-tpu-inference-cloud-next๐ŸŸ  (single secondary; treat as rumor)

Technical Trajectory

  • Cadence: roughly annual โ€” v5e/v5p (2023) โ†’ v6e Trillium (2024/25) โ†’ v7 Ironwood (announced 2025, GA into 2026). Google now leads with an inference-first framing ("age of inference", blog.google, ๐ŸŸข).
  • Compute jump: Trillium 918 TF BF16 โ†’ Ironwood 2,307 TF BF16 (2.5x) and 4,614 TF FP8 โ€” first TPU generation with headline FP8 (๐ŸŸข, official docs).
  • Memory: 32 GB โ†’ 192 GB HBM3e per chip (6x) at 7.37 TB/s; closes the capacity gap with B200-class GPUs (๐ŸŸข).
  • Scale: pod size step from 256 (v6e) to 9,216 chips (TPU7x) with optical circuit switching heritage; Google's differentiation is pod-scale fabric, not single-chip FLOPs (๐ŸŸข docs; pod EF figure is vendor marketing ๐ŸŸก).
  • Node: process node undisclosed for both generations (n/a); external visibility comes via Broadcom earnings commentary (see custom-asic.md).
  • Availability model: internal-first (Gemini training/serving) plus external Cloud GA โ€” the only custom ASIC with meaningful third-party rental, making TPU the cleanest public test of CLAIM-AI-SILICON-001.

Watch Items

  • Any official TPU v8 disclosure (Cloud Next / Hot Chips 2026) โ€” upgrade or kill the ๐ŸŸ  rumor row.
  • MLPerf Training/Inference submissions using Ironwood (Google has submitted TPU results in past rounds; none verified for v5.1 this pass).
  • Ironwood external capacity signals: region availability expansion, committed-use pricing changes on Google Cloud pricing pages (A4).
  • Alphabet earnings commentary quantifying TPU fleet share vs GPU purchases.

Claims

  • CLAIM-AI-SILICON-001 โ€” primary evidence stream: TPU is the largest and most externally visible custom-ASIC program taking share of accelerator compute vs merchant GPU.
  • CLAIM-AI-BOTTLENECK-001 โ€” TPU HBM3e demand and OCS-based pod fabric are inputs to the memory/packaging bottleneck picture.

Sources

Changelog

  • 2026-07-10: Created; first verification pass.