Series — Accelerator Spec Matrix
Owner: Finance / Charlie AGT-002 Source ID: SRC-AI-VENDOR-SPECS (vendor spec pages / whitepapers), SRC-AI-CNINFO-FILINGS (China stack) Unit: mixed — process node, memory GB, bandwidth TB/s, dense FLOPs by precision, TDP W, interconnect GB/s Cadence: event-driven (launches) + quarterly sweep Visibility: PUBLIC As-of convention: every row carries the as-of date the spec was verified and a source grade; peak FLOPs must state precision (and sparsity if applicable)
How to append: one row per chip per verification pass. When a vendor revises a spec (e.g. memory config bump), append a NEW row with the new as-of date — do not edit old rows. Status values: shipping | announced | rumored (rumored rows require grade 🟠 or worse and are excluded from public claim support).
| As-of | Vendor | Chip | Status | Node | Memory (type / GB / TB/s) | Dense FLOPs (precision) | TDP (W) | Scale-up interconnect | Source | Grade |
|---|---|---|---|---|---|---|---|---|---|---|
| 2026-07-10 | NVIDIA | B300 (Blackwell Ultra, in GB300 NVL72) | shipping | TSMC 4NP | HBM3e / 288 / 8.0 | 15 PF dense FP4 (NVFP4) per GPU; rack: 1,080 PF dense FP4, 720 PF FP8/FP6 (sparsity basis per spec page) | n/a (secondary reports ~1,400) | NVLink 5 — 1.8 TB/s per GPU; 130 TB/s aggregate per NVL72 rack | https://www.nvidia.com/en-us/data-center/gb300-nvl72/ + https://developer.nvidia.com/blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/ | 🟢 |
| 2026-07-10 | NVIDIA | Rubin GPU (Vera Rubin NVL144) | announced (CES 2026 "full production"; ramp 2H2026) | TSMC 3nm-class (press) | HBM4 / up to 288 / 22 (vendor keynote) | 50 PF NVFP4 inference, 35 PF NVFP4 training per GPU (vendor; dense/sparse basis not stated) | n/a | NVLink 6 (2x per-link vs NVLink 5, vendor); NVL144 rack: 3.6 EF NVFP4 | https://www.servethehome.com/nvidia-launches-next-generation-rubin-ai-compute-platform-at-ces-2026/ + https://www.tomshardware.com/pc-components/gpus/nvidias-vera-rubin-platform-in-depth-inside-nvidias-most-complex-ai-and-hpc-platform-to-date | 🟡 (keynote via credible secondary; official spec page pending) |
| 2026-07-10 | AMD | Instinct MI355X | shipping | TSMC 3nm + 6nm chiplets (CDNA 4) | HBM3E / 288 / 8.0 | 5.0 PF dense FP8 (10.1 PF w/ 2:4 sparsity); 10.1 PF FP4 (MXFP4); 2.5 PF dense FP16 | 1,400 (TBP, liquid-cooled) | Infinity Fabric — 7 links x 153 GB/s | https://www.amd.com/en/products/accelerators/instinct/mi350/mi355x.html | 🟢 |
| 2026-07-10 | AMD | Instinct MI455X (Helios rack) | announced (CES 2026; 2H2026) | TSMC N2 compute chiplets (press) | HBM4 / 432 / 19.6 (vendor) | 40 PF FP4, 20 PF FP8 per GPU (vendor; dense/sparse basis not stated) | n/a | Helios rack: 72x MI455X; 2.9 EF FP4 per rack (vendor) | https://www.amd.com/en/newsroom/press-releases/2026-1-5-amd-and-its-partners-share-their-vision-for-ai-ev.html + https://www.tomshardware.com/tech-industry/artificial-intelligence/amd-touts-instinct-mi430x-mi440x-and-mi455x-ai-accelerators-and-helios-rack-scale-ai-architecture-at-ces-full-mi400-series-family-fulfills-a-broad-range-of-infrastructure-and-customer-requirements | 🟡 (announcement; official datasheet pending) |
| 2026-07-10 | TPU v7 Ironwood (TPU7x) | shipping (GA on Google Cloud) | n/a (not disclosed) | HBM3e / 192 / 7.37 | 4.614 PF FP8, 2.307 PF BF16 per chip (peak, per official docs; sparsity not stated) | n/a | ICI 1.2 TB/s bidirectional per chip; pods to 9,216 chips | https://docs.cloud.google.com/tpu/docs/tpu7x + https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/ironwood-tpu-age-of-inference/ | 🟢 | |
| 2026-07-10 | TPU v6e Trillium | shipping | n/a (not disclosed) | HBM / 32 / 1.64 | 918 TF BF16, 1,836 TOPS INT8 per chip | n/a | ICI 800 GB/s bidirectional per chip; 256-chip pod (2D torus) | https://docs.cloud.google.com/tpu/docs/v6e | 🟢 | |
| 2026-07-10 | Huawei | Ascend 910C | shipping | SMIC N+2 7nm-class (secondary) | HBM / 128 / n/a | ~800 TF FP16 (secondary; dense/sparse basis not stated) | n/a | CloudMatrix 384: 384 chips on Unified Bus fabric, ~48 TB HBM per system (secondary) | https://xpu.pub/2025/04/22/huawei-ascend/ + https://chinaresearchcollective.substack.com/p/huawei-ascend-cloudmatrix-384-supernode | 🟡 (no official spec sheet published) |
| 2026-07-10 | Huawei | Ascend 950PR (Atlas 350 card) | shipping (launched 2026-03; volume ramp 2H2026 per press) | n/a (press: SMIC 5nm-class N+3, unverified) | HiBL 1.0 in-house HBM / n/a (secondary reports conflict, 112-144 GB) / n/a | n/a (vendor keynote claims ~1 PF FP8, ~2 PF FP4 for Ascend 950 series; basis not stated, unverified) | n/a | UB interconnect; vendor claims 2.5x 910C interconnect bandwidth | https://www.huaweicentral.com/huawei-reveals-3-year-ascend-ai-chip-roadmap-950-coming-in-2026/ + https://www.digitimes.com/news/a20251226PD222/huawei-ascend-nvidia-2025-market.html | 🟡 |
| 2026-07-10 | Huawei | Ascend 950DT | announced (late 2026 per roadmap) | n/a | HiZQ 2.0 in-house HBM / 144 / 4.0 (keynote via secondary) | n/a (adds FP8 / MXFP8 / HiF8 / MXFP4 / HiF4 formats per keynote) | n/a | n/a | https://convequity.substack.com/p/huawei-ascend-ai-chip-roadmap-and + https://www.huaweicentral.com/huawei-reveals-3-year-ascend-ai-chip-roadmap-950-coming-in-2026/ | 🟡 |
| 2026-07-10 | Cambricon | Siyuan MLU590 | shipping | SMIC 7nm-class N+2 (secondary) | HBM / n/a / n/a | n/a (vendor publishes no spec sheet) | n/a | n/a | https://www.tomshardware.com/tech-industry/semiconductors/cambricon-targets-500000-ai-chips-in-2026-as-china-accelerates-domestic-hardware-push | 🟡 (revenue is filings-visible; chip specs are not) |
| 2026-07-10 | Cambricon | Siyuan MLU690 | rumored (mass production targeted 2026 per press) | n/a | n/a | n/a | n/a | n/a | https://www.tomshardware.com/tech-industry/semiconductors/cambricon-targets-500000-ai-chips-in-2026-as-china-accelerates-domestic-hardware-push | 🟠 (no vendor disclosure) |
| 2026-07-10 | Cerebras | WSE-3 (CS-3 system) | shipping | TSMC 5nm | on-wafer SRAM / 44 / n/a (21 PB/s on-chip per secondary) | 125 PF peak (vendor "AI compute"; precision/sparsity basis not stated on chip page — not comparable until qualified) | n/a | clusters to 2,048 CS-3 nodes; MemoryX external memory 1.5 TB to 1.2 PB | https://www.cerebras.ai/chip + https://www.cerebras.ai/press-release/cerebras-announces-third-generation-wafer-scale-engine | 🟢 (vendor page; missing precision qualifier flagged) |
| 2026-07-10 | AWS (Annapurna) | Trainium3 | shipping (GA 2025-12-02) | 3nm-class (press) | HBM3e / 144 / 4.9 | 2.52 PF FP8 (MXFP8) per chip | n/a | NeuronSwitch-v1 all-to-all; Trn3 UltraServer to 144 chips (362 PF FP8, 20.7 TB HBM3e) | https://aws.amazon.com/about-aws/whats-new/2025/12/amazon-ec2-trn3-ultraservers/ + https://aws.amazon.com/ai/machine-learning/trainium/ | 🟢 |
| 2026-07-10 | AWS (Annapurna) | Trainium2 | shipping | n/a | HBM / 96 / n/a (secondary) | n/a (AWS states Trainium3 = 2x Trainium2 MXFP8 throughput) | n/a | NeuronLink; Trn2 UltraServer 64 chips | https://aws.amazon.com/ai/machine-learning/trainium/ | 🟡 (official page lacks per-chip Trn2 sheet) |
| 2026-07-10 | Microsoft | Maia 200 | shipping (deployed 2026-01, Azure US Central) | TSMC 3nm | HBM3e / 216 / 7.0 (+272 MB on-chip SRAM) | >10 PF FP4, >5 PF FP8 per chip (vendor; dense/sparse basis not stated) | 750 (SoC TDP) | Ethernet-based two-tier scale-up, 2.8 TB/s bidirectional per accelerator; clusters to 6,144 | https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/ | 🟢 |
| 2026-07-10 | Meta | MTIA v2 | shipping (internal ranking/recommendation inference) | TSMC 5nm | LPDDR5 / 128 / 0.205 (+256 MB SRAM at 2.7 TB/s) | 354 TF dense INT8, 177 TF dense BF16 (708 / 354 with sparsity) | 90 | n/a | https://ai.meta.com/blog/next-generation-meta-training-inference-accelerator-AI-MTIA/ | 🟢 |
| 2026-07-10 | Meta | MTIA 300-500 (roadmap) | announced (deployment through 2027 per press) | 3nm + CoWoS reported | n/a | n/a | n/a | n/a | https://www.tomshardware.com/tech-industry/semiconductors/custom-ai-asics-examined-from-broadcom-to-mtia | 🟡 |