Board — Accelerator Silicon (GPU / TPU / ASIC / Wafer-Scale)
Status: active Owner: Finance / Charlie AGT-002 Board ID: BOARD-AI-SILICON Visibility: PUBLIC Last updated: 2026-07-10
Purpose
Track the technical trajectory of AI accelerator silicon — architectures, roadmaps, measured performance, and cost curves — across the merchant GPU incumbents, hyperscaler in-house ASICs, the China domestic stack, and wafer-scale challengers.
Methodology (SemiAnalysis-inspired, public-primitives version): follow the physical primitives — process node, memory type/bandwidth, packaging, scale-up/scale-out interconnect, rack power — from PUBLIC primary sources only (vendor spec pages, architecture whitepapers, MLCommons results, listed-company filings). Spec-sheet numbers are commitments (A2); measured benchmark results and shipment/revenue disclosures are throughput (A3); street pricing and rental rates are price signals (A4).
This board's pages are approved PUBLIC (Hugo, 2026-07-10): technical facts and source-graded tables only. Investment implications, share forecasts, and portfolio linkage stay MEMBERS/INTERNAL elsewhere.
Coverage
| Entity page | Scope |
|---|---|
../entities/nvidia.md | Merchant GPU incumbent — architecture cadence, HBM/interconnect roadmap |
../entities/amd.md | Merchant GPU challenger — Instinct line, ROCm maturity signals |
../entities/google-tpu.md | Hyperscaler in-house ASIC — TPU generations, internal + external availability |
../entities/huawei-ascend.md | China stack lead — Ascend series, SMIC node constraint, cluster-scale workaround |
../entities/cambricon.md | China merchant accelerator — listed (688256.SH), filings-visible revenue |
../entities/cerebras.md | Wafer-scale challenger — WSE generations, inference-as-a-service pivot |
../entities/custom-asic.md | Broadcom/Marvell co-designed hyperscaler ASICs (Trainium, Maia, MTIA, etc.) |
Tracked Series
| Series | Unit | Source ID | Cadence | Series file |
|---|---|---|---|---|
| Accelerator spec matrix | node / GB / TB/s / FLOPs / W | SRC-AI-VENDOR-SPECS | Event (launches) + quarterly sweep | ../../series/accelerator-specs.md |
| Measured benchmarks | MLPerf results, tokens/s/chip | SRC-AI-MLCOMMONS | Per MLPerf round (~2/yr) + event | ../../series/accelerator-benchmarks.md |
| Roadmap cadence | months between generations per vendor | SRC-AI-VENDOR-SPECS | Event | (derived in this board page) |
| China stack shipments/revenue | CNY revenue, units where disclosed | SRC-AI-CNINFO-FILINGS | Quarterly filings | ../../series/accelerator-specs.md (rows) + china-ai-stack board |
Primary Sources
- Vendor spec pages / architecture whitepapers (NVIDIA, AMD, Google Cloud, Huawei, Cambricon IR, Cerebras) — Primary
- MLCommons (MLPerf Training/Inference) results tables — Primary
- Listed-company filings: Cambricon 688256.SH (cninfo), TSMC/SK Hynix calls for node/HBM context — Primary
- SemiAnalysis FREE posts — Secondary (never paywalled content; client-conflict caveat)
- Hot Chips / ISSCC papers — Primary for architecture detail
Current Claims
- CLAIM-AI-SILICON-001 — custom-ASIC share of accelerator compute rising vs merchant GPU (watch)
- CLAIM-AI-SILICON-002 — China domestic stack node gap vs frontier, and the cluster-scale/chiplet workaround path (watch)
- Related: CLAIM-AI-BOTTLENECK-001 (pricing power sits at the current bottleneck)
Noise Rules
- Ignore un-dated "next-gen chip will be Nx faster" claims without a spec sheet or paper (A1 narrative — log nothing).
- Peak-FLOPs marketing without precision/sparsity qualifiers is not comparable data; record only with precision noted.
- Do not infer China-stack parity from single benchmark demos; require reproducible results or filings-visible revenue.
- Vendor "orders/backlog" leaks are not shipments; only filings and disclosed shipments count as A3.